1. Field of the Invention
This invention relates to integrated circuit fabrication processes, and in particular, to a method of providing self-aligned metal silicide layers on bipolar integrated circuits which circuits also include self-aligned polycrystalline silicon features such as electrodes.
2. Description of the Prior Art
The technology for fabricating bipolar integrated circuits has advanced dramatically in the past several years. Methods are now well-known for fabricating regions of oxidized semiconductor material to electrically isolate bipolar circuits fabricated in a single substrate. One such technique is taught by Douglas Peltzer in U.S. Pat. No. 3,648,125 entitled "Method of Fabricating Integrated Circuits With Oxidized Isolation and the Resulting Structure". That patent teaches a technique by which epitaxial pockets of semiconductor silicon may be electrically isolated by the formation of surrounding regions of oxidized semiconductor material in conjunction with underlying buried layers.
Also well-known are self-aligned polycrystalline silicon processes in which active device regions and contacts to such regions, as well as for other purposes, are formed by deposition of polycrystalline silicon over a substrate. Following the deposition suitable treatment, typically heating, causes impurities from the polycrystalline silicon to diffuse into the substrate to form regions, such as emitters, which have self-aligned doped polycrystalline silicon contacts. See, for example, "A New Polysilicon Process For a Bipolar Device-PSA Technology," by Okada et al., IEEE Journal Of Solid-State Circuits, Vol. SC-14, No. 2, April 1979, at page 307. A partially self-aligned MOS titanium silicide process is disclosed by Murao et al. in "A High Performance CMOS Technology with Ti-Silicided P/N-Type Poly-Si Gates," IEEE International Electron Devices Meeting 1983, pgs. 518-521.
Prior art processes for fabricating bipolar integrated circuits having self-aligned polycrystalline silicon electrodes and layers of metal silicide to provide interconnections, however, suffer from several disadvantages. First, because the dopant used to fabricate the base contact, emitter, and other regions, must be contained in the polycrystalline silicon if the polysilicon electrodes are to be self-aligned, the dopant is prone to migrate into the overlying layers of metal silicide during the thermal processes used to diffuse the dopant. Secondly, because such prior art processes do not provide metal silicide self-aligned to the polysilicon regions to be contacted, an etching step must be performed to remove undesired regions of metal silicide from the wafer. This step is not only undesirable because of the extra process complexity, but also because it leaves traces of unetchable conductive residues on the field oxide areas. These traces increase the emitter-base and collector-base junction leakages, thereby substantially degrading circuit performance. Furthermore, because such prior art processes typically required long annealing treatments to lower sufficiently the resistance of the fabricated metal silicide layers, metal oxidation and incorporation of oxygen into the silicide film were common occurrences.
It is therefore an object of this invention to provide a process for fabricating metal silicide layers on desired components of bipolar circuits which process is self-aligned to the components, which does not result in the movement of dopants from polysilicon into the silicide, which eliminates metallic contaminants from the surface of the field oxide surrounding active device areas, and which eliminates the need for etching the metal silicide.